Rambus PCIe 7.0 Switch IP Boosts Bandwidth and Scalability for AI and HPC Applications
May 06, 2026
News
Rambus introduced its Rambus PCIe 7.0 Switch IP with Time Division Multiplexing (TDM) engineered to meet industrial challenges such as escalating bandwidth, latency, and scalability requirements of AI, cloud, and high-performance computing (HPC) systems.
“The acceleration of AI is fundamentally reshaping system architectures, and it’s no longer sufficient to simply add more lanes or more endpoints,” said Simon Blake‑Wilson, senior vice president and general manager of Silicon IP at Rambus. “With our PCIe 7.0 Switch IP with TDM, Rambus is giving system architects a new degree of freedom to scale bandwidth efficiently and deterministically, while reducing complexity and improving overall system utilization. This is a critical enabler for scale up and scale out of the next wave of advanced AI clusters and HPC networks.”
The switch IP is enhanced for next‑generation AI and data center SoCs that demand maximum bandwidth density, advanced traffic management, and seamless scalability. TDM capabilities allow developers to intelligently schedule and multiplex traffic across shared links, helping increase fabric use while supporting various workload profiles, from large‑scale AI training to latency‑sensitive inference and data movement.
Rambus designed the solution to integrate seamlessly into leading-edge ASIC platforms and to collaborate with Rambus’ existing PCIe 7.0 IP portfolio, including controllers, retimers, and debug solutions.
For more information, visit rambus.com/.
Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.
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Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.
