Rambus Unveils DDR5 9600 RDIMM Chipset for Next-Generation AI and HPC Workloads

By Chad Cox

Production Editor

Embedded Computing Design

July 09, 2026

News

Rambus Unveils DDR5 9600 RDIMM Chipset for Next-Generation AI and HPC Workloads
Image Credit: Rambus

Rambus introduced its DDR5 9600 Server RDIMM chipset Built around the new Rambus 6th Generation Registering Clock Driver (RCD06) with a 20 percent increase in bandwidth over the previous generation. The chipset enables RDIMMs, operating up to 9600 MT/s, unlocking the bandwidth and capacity commanded by agentic AI, high-performance computing (HPC), and other data-intensive workloads.

“The rapidly accelerating adoption of agentic AI and AI inference workloads is driving unprecedented demand for higher memory bandwidth and capacity in the data center,” said Rami Sethi, SVP and general manager of Memory Interface Chips at Rambus. “With our DDR5 9600 RDIMM chipset featuring the new RCD06, Rambus continues to extend its leadership in high-speed memory interface solutions, enabling our customers to deliver the performance and reliability required for next-generation server platforms.”

The chipset includes the PMIC5030 power management IC delivering efficient, high-current power at low voltage levels to support advanced DDR5 RDIMM configurations. It comes with a Serial Presence Detect (SPD) Hub with an integrated temperature sensor, as well as dedicated Temperature Sensor ICs for critical module telemetry, configuration, and thermal monitoring functions.

Utilizing its integrated clocking, control, and power management, the solution supports signal and power integrity at high data rates, reducing design complexity for memory module manufacturers and improving system dependability.

For more information, visit rambus.com/blogs/enabling-next-generation-data-center-infrastructure-for-agentic-ai-introducing-the-rambus-ddr5-9600-server-rdimm-chipset/.

Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.

He is well versed in many facets of industrial computing including Edge AI, IoT, Processing, Security, Open Source, and more.

Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.

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